1. Field of the Invention
The present invention relates to processor systems generally and, more specifically, to a local bus bridge for interfacing between different processor bus architectures.
2. Description of the Related Art
Network processors are generally used for analyzing and processing packet data for routing and switching packets in a variety of applications, such as network surveillance, video transmission, protocol conversion, voice processing, and internet traffic routing. Early types of network processors were based on software-based approaches with general-purpose processors, either singly or in a multi-core implementation, but such software-based approaches are slow. Further, increasing the number of general-purpose processors had diminishing performance improvements, or might actually slow down overall Network Processor throughput. Newer designs add hardware accelerators to offload certain tasks from the general-purpose processors, such as encryption/decryption, packet data inspections, etc.
Because of the complexity of network processors and other system-on-chip (SoC) architectures, there is usually more than one kind of processor bus implemented on the chip, especially if there is a mixture of processor designs on the chip. Generally, one or more processors to communicate with external peripherals, memory, or each other using a processor bus. However, processor buses are not standardized and each processor design utilizes a different, incompatible, bus structure and protocol. Nonetheless, data and addresses need to be passed between buses using a bus “bridge”. Because of the incompatibility of the buses, delays and other inefficiencies in the conveyance of data and commands from one bus to the other might be detrimental to operation of the chip as a whole. Thus, it is desirable to provide a bus bridge that efficiently interfaces between two different bus designs, each with their own transaction ordering rules, with command ordering.